A NAND type semiconductor memory device, which includes three-dimensionally disposed memory cells, includes a plurality of electrode layers stacked on a substrate, semiconductor channel bodies extending through the electrode layers and a conductive layer provided in the substrate. Such a semiconductor memory device includes memory cells and selection transistors provided along each semiconductor channel bodies. Thus, when impurity doping into the semiconductor channel bodies is performed so as to set threshold voltages of the selection transistors at a desirable value, there may be a reduction of cell current while reading data out from the memory cells.